A Simulation Study of Variability in Gate-all-Around Nanosheet Transistors

Sammanfattning

Gate-all-around (GAA) nanosheet field effect transistors (NSFETs) seem to be one of the most promising replacement options for FinFETs towards scaling down below to the sub-7nm technology nodes. They offer better electrostatics and control of short channel effects (SCEs) due to their superior control over the channel and their large effective channel width. Moreover, one can vertically stack multiple nanosheets to improve the drive strength of the device at a much-relaxed geometry than an aggressively scaled FinFET. However, stacking nanosheets would result in complex device structure, leading to significant process variability. Process variations could arise from irregular sheet thicknesses, random doping fluctuations, strain-induced variability, temperature effects, etc. which would affect the performance of the device. This has put a great emphasis on the need to come up with a properly calibrated process and simulation tools to analyze the performance of the NSFETs by identifying the sources of process variations with utmost precision. For this purpose, a TCAD-based simulation assessment has been done to model the design and performance of GAA NSFETs. The study explores the impacts of the variation in various physical parameters including the number of nanosheets, the sheet thickness, the work-function (WF) of metal gate stack layers, operational temperatures and channel doping on the electrical performance of the NSFETs. Moreover, a detailed fabrication process simulation flow for the design of a 3-sheet GAA NSFET has been presented. The simulation results predict that the process variations primarily have an impact on the device threshold voltage (Vth) which in turn influences the on-off currents, and the sub-threshold swing of the device. A comparative analysis has been done to understand the deviation of these electrical characteristics from their ideal values as a result of these variations.