Accuracy and Hardware Cost Analysis of Multi-Format Floating-Point Arithmetic Generated by FloPoCo on FPGA

Sammanfattning

Modern artificial intelligence (AI) and digital signal processing (DSP) workloadsare highly data-driven and computationally demanding, relying heavily on massivemultiply-accumulate (MAC) operations. While standard IEEE 754 floating-pointarithmetic provides a vast dynamic range, its strict compliance requirements, suchas subnormal handling and exact rounding, incur significant hardware overhead.To address this, this thesis evaluates the accuracy and hardware cost of multiformat floating-point arithmetic generated by the FloPoCo framework on fieldprogrammable gate arrays (FPGAs). We employ a hardware-software co-simulationmethodology, combining Xilinx Vivado for power, performance, and area assessmentwith a Python-based error evaluation engine using Gaussian distributed test vectorsto emulate AI workloads.Our results demonstrate that FloPoCo’s custom Nfloat format, which eliminatessubnormal support and utilizes a dedicated exception field, significantly reducespipeline depth, look-up table (LUT) consumption, and dynamic power compared toIEEE 754 implementations across all tested bit-widths. Furthermore, a comparativeanalysis between a unified-precision Nfloat MAC and an IEEE fused multiply-add(FMA) reveals that the NFloat MAC achieves over 50% power and area savingswhile maintaining identical algorithmic fidelity at low-to-medium precisions. Finally, we investigate the performance of mixed-precision MAC architectures in deepaccumulation chains with lengths up to 5120 accumulation steps. The results showthat mixed-precision computation effectively maintains a stable relative error near0.001%. FloPoCo and the Nfloat format present a efficient and customizable alternative for FPGA-based high-performance computing.