Automated Generation of Configurable CNN IPs using Serial Coding

Sammanfattning

In recent years, significant progress has been made in the field of artificial intelligence, particularly in neural networks, due to increased computing power and available data. This development has created the need for new platforms on which to implement these networks, which differ from traditional platforms, such as CPUs and GPUs. This change is sometimes made in an attempt to reduce resources, time, or energy based on the specific application’s needs. Field-programmable gate arrays (FPGAs) are a good alternative for using neural networks in edge computing, but developing the necessary hardware is costly and complex. Therefore, this thesis focuses on creating an automatic convolutional neural network (CNN) compiler that generates a hardware system from a software description. Several objectives guided this approach: first, to reduce the time it takes to design a CNN architecture for hardware; and second, to create different models with the same hardware design to assess its performance in various areas. We begin with a design that prioritizes reducing area and latency. Thanks to this automatic compiler, we can test this design’s effectiveness for different CNN architectures, helping us better understand the original design’s benefits and limitations. We created a functional Python compiler that takes networks described in PyTorch and Brevitas and generates the corresponding VHDL code to implement those networks in a Xilinx FPGA. Using this tool, we generated up to 12 different CNN models and measured their accuracy, latency, power consumption, and resource utilization. We generated some of these models with the LeNet-5 architecture to compare it with existing implementations of the same architecture and verify that our design significantly reduces area compared to other approaches.