Design of a Kolmogorov-Arnold Network Hardware Accelerator

Sammanfattning

The exponential growth of Big Data, the Internet of Things (IoT), and Large Language Models (LLMs) has significantly increased the computational and energy demands of modern computing systems. In response, research has increasingly focused on alternative machine learning paradigms and hardware architectures that reduce model complexity and computational load. One such paradigm is the Kolmogorov-Arnold Network (KAN), a novel neural architecture that replaces conventional trainable weights with B-spline-based activation functions. This thesis presents one of the first comprehensive hardware implementations of KAN inference. To maximize performance, several algorithmic optimizations are introduced, including quantization techniques for static grid B-splines and simplified Look-Up Tables (LUTs) for basis function evaluation. An inference algorithm is developed to exploit the inherent sparsity of B-spline activations through dynamic coefficient bypassing, substantially reducing both memory bandwidth requirements and the number of operations. On the hardware side, the design features a dedicated Comparator Chain for grid interval detection, a memory layout optimized for sequential coefficient access, and a Processing Element (PE) architecture for first-order B-spline evaluation. The full system is implemented as a custom accelerator integrated with a RISC MicroBlaze processor on a Xilinx Artix-7 FPGA. Experimental results confirm functional correctness and demonstrate trade-offs in performance, area, and scalability. This work lays the foundation for future exploration of KAN-based models in resource-constrained hardware, offering a scalable platform for spline-driven machine learning.