Early Power Estimation of JESD204D Link Layer : Using SystemC TLM2.0

Sammanfattning

Power estimation is critical in the early stages of embedded system design, offering insights into energy consumption patterns and enabling designers to optimize system performance. However, current power estimation methodologies typically suffer from several limitations that restrict their effectiveness in practical industrial scenarios. First, existing power estimation techniques are predominantly carried out in the later stages of system design. Second, while Transaction-Level Modeling (TLM) methods enable earlier estimation, they often utilize oversimplified power models, resulting in limited accuracy. Third, many early-stage methodologies lack robust automation and scalability, restricting their practical applicability. This issue becomes particularly prominent with complex hardware designs like the JESD204D protocol used in high-speed communication systems, which involve sophisticated algorithmic and structural complexities. To address these challenges, this thesis proposes a comprehensive double- framework methodology integrating SystemC TLM2.0 modeling with two complementary tools: Powersim, for early high-level power estimation, and Catapult Ultra, providing RTL-level reference data. The objective is to bridge the gap between algorithm-level modeling and detailed RTL analysis, enabling more accurate, scalable, and efficient early-stage power estimation. By comparing results obtained from Powersim-based transaction-level modeling (TLM) with Catapult-generated RTL power estimations, this study investigates the effectiveness and accuracy of a hybrid early power estimation approach. The outcomes demonstrate the potential to achieve significant improvements in power estimation accuracy during the early design phases, thus providing valuable insights and decision support for power optimization. Future work involves refining computational operator models, integrating artificial intelligence (AI)-driven dynamic prediction mechanisms, and enhancing methodology adaptability to accommodate complex, diverse hardware architectures.