Exploration of a Dynamic Approximate Multiplier for Mixed-Precision Inference

Sammanfattning

The increasing demand for efficient neural network (NN) inference on edge devices has driven the need for hardware-level optimizations that balance computational accuracy with energy and area efficiency. This thesis explores the design and implementation of a dynamic approximate multiplier capable of mixed-precision inference, focusing on floating-point (FP) formats. Using a logarithmic-approximation approach, we implement three precision modes—High Precision Correction (HPC), Low Precision Correction (LPC), and No Correction (NC)—and evaluate their performance on Artix-7 FPGA hardware. Our results indicate that at 8-bit widths, the numerical error difference between full precision and approximate modes gives a manageable drop off in NN image classification accuracy. Hardware synthesis shows that 8-bit NC and LPC multipliers provide significant advantages in area (number of LUTs) and latency compared to commonly used 8-bit fixed-point multipliers. Furthermore, we demonstrate that a mixed-precision strategy, guided by layer-wise sensitivity, allows for maximizing hardware efficiency while maintaining nearly baseline accuracy. We conclude that approximate 8-bit floating-point multipliers are in some cases a viable alternative to fixed-point arithmetic.