Integrating Artificial Intelligence in Circuit Design with Large Language Models

Sammanfattning

Modern circuit design is a complex, expertise-driven process often involving time-consuming workflows and extensive manual effort. This thesis explores the feasibility of applying Large Language Model (LLM)s to automate parts of this process, focusing on generating circuit netlists from natural language specifications. In collaboration with ABB Robotics, the thesis investigates how smaller, open-source LLM can be fine-tuned using limited data and computational resources, to increase efficiency, reduce tedious repetitive tasks and to explore the possibilities of LLMs. Multiple training configurations were tested, and the performance of a LLM was evaluated using four different train/test splits: 95/5, 90/10, 85/15, and 80/20. For each split, six configurations were compared, the base model, the base model with Retrieval-Augmented Generation(RAG), a Quantized Low-Rank Adaptation (QLoRA) fine-tuned model, a QLoRA fine-tuned model with RAG, a Low-rank Adaptation (LoRA) fine-tuned model, and a LoRA fine-tuned model with RAG. Despite the promise of LLMs in code and text generation tasks, experimental results showed limitations in the models’ ability to produce syntactically correct and functionally valid netlists. While some improvement was found through fine-tuning, the overall performance remained insufficient for practical deployment. RAG did not show the expected improvements to the generations. The findings showed both the potential and the current challenges of using LLM in Electronic Design Automation (EDA), highlighting the importance of acquiring more focused data, developing specialised architectures for specific domains, and improving training techniques. The work serves as an initial step toward understanding how generative AI can support circuit design and outlines areas for future research.