Modularity, Scalability, Reusability, Configurability, and Interoperability of ASIC/FPGA Verification IP

Sammanfattning

The complexity of chip design has been exponentially rising, resulting in increased complexity and costs in chip verification. This rise in complexity results in increased time to market and increases risks of chip in fabrication, that can be catastrophic and result in major losses. For this reason, it is necessary for companies to ensure the verification testbenches used are predictable and reusable. The SystemVerilog language is a Hardware Verification Language that adopts the object-oriented principles. It is a highly suitable language for verification environments as it offers functional coverage, constrained random testing and assertions. The Universal Verification Methodology package consists of SystemVerilog libraries used for the industry grade verification environments. The Universal Verification Methodology takes advantages of features and design patterns from software engineering in general and Object-oriented Programming in particular, such as data hiding to raise the level of abstraction, generic programming to increase reusability, polymorphism for inter-operability, etc. There is a lot of pressure on the performance of today’s verification teams. This thesis develops a functional verification environment for the Avalon Streaming Interface while incorporating design practices that make the environment far more robust and reusable. The study focuses on instilling properties in the Verification environment that help save verification time.