Multi-Core Microprocessor Load/Performance Optimization

Sammanfattning

Software now defines a substantial portion of the functionality in modern electric powertrains. Inverter control units, which regulate power delivery to electric machines, must execute complex control algorithms under strict real-time constraints while interacting directly with high-frequency switching hardware. Even small deviations in execution time or scheduling jitter can degrade control precision, reduce efficiency, or violate safety requirements [1; 2]. As electric vehicles integrate more diagnostics, monitoring, and safety functions, the computational load on embedded microcontrollers continues to increase [3; 4]. These systems are typically deployed on multi-core automotive microcontrollers such as the Infineon AURIX TC3xx microcontroller featuring three TriCore CPUs, each with private DSPR memory and access to a shared Fast LMU region, which provide heterogeneous memory regions, hardware accelerators, and deterministic peripheral interfaces. While these platforms offer significant capability, achieving predictable execution remains challenging. Model-based development environments such as Simulink accelerate algorithm design but often generate code that is not optimised for embedded execution [5; 6]. In parallel, AUTOSAR Classic introduces modularity and portability but can also introduce overheads through fragmented memory allocation, rigid task structures, and limited visibility into low-level timing behaviour [7; 8]. Target System Context. The optimisation work in this thesis is performed on a production-grade AUTOSAR-based inverter control stack running on a Infineon AURIX TC3xx microcontroller featuring three TriCore CPUs, each with private DSPR memory and access to a shared Fast LMU region. The platform provides three TriCore CPUs and a heterogeneous memory hierarchy consisting of core-local DSPR regions and a shared Fast LMU. The control software implements a conventional field-oriented control (FOC) pipeline executed in a high-priority 1 ms PWM-synchronous loop. Each control period performs: (i) ADC acquisition of phase currents and DC-link quantities, (ii) signal conditioning, (iii) Clarke and Park transforms, (iv) d/q-axis PI current regulation, (v) inverse Park transformation, (vi) space-vector PWM modulation, and (vii) PWM register update. Lower-priority 10 ms and 100 ms tasks handle diagnostics, monitoring, and housekeeping. In the baseline system, ADC sampling is performed by a CPU-driven ISR. In the optimised design, sampling is offloaded to a DMA engine configured in ping-pong (double-buffer) mode, writing directly into DSPR memory. DMAcompletion is handled by a minimal ISR that enqueues buffer indices into a lockless single-producer/single-consumer (SPSC) ring, decoupling acquisition from the computationally heavy control tasks Arithmetic and memory optimisations are applied selectively across the chain: hot kernels such as the Clarke–Park transforms and PI controllers are migrated to fixed-point arithmetic using mixedQ-formats (Q31 and Q15) selected through range analysis (see Section 3.4), while trigonometric operations use a hybrid CORDIC/LUT approach. Runnable-to-task mapping and activation phasing are refined to reduce instantaneous CPU demand and improve timing determinism. Introducing the system context early clarifies the architectural constraints, timing sensitivities, and computational structure that motivate the optimisation strategies developed in this thesis