Porting PX4 to a Heterogeneous Microcontroller : Architecture Patterns and Trade-offs for On-Chip NPU Acceleration

Sammanfattning

Background. Unmanned Aerial Vehicles (UAVs) increasingly run AI workloadssuch as visual perception and obstacle avoidance. Conventional architectures isolatethese workloads on companion computers, introducing interoperability complexity,communication overhead, and additional failure modes. Microcontrollers that integrate a Neural Processing Unit (NPU) on the same die as the flight-control core,such as the STM32N6 (Cortex-M55 + Neural-ART NPU), make single-core processor integration physically possible, but the software-architectural feasibility forsafety-critical flight control remains unclear.Objectives. The aim is to design, implement, and empirically evaluate softwarearchitecture artefacts that integrate NPU acceleration into a microcontroller-classflight controller, and to characterise the resulting trade-offs between Performance,Interoperability, and Availability.Methods. A Design Science Research (DSR) study is conducted, complementedby a snowballing systematic literature review of 50 primary studies. PX4 is portedfrom the Cortex-M7 STM32H743 to the STM32N6, and an NPU-backed PX4 modulerunning a YOLOv8n model is integrated into PX4’s uORB publish–subscribe busthrough a layered driver. The artefact is evaluated through a 1,206-flight HardwareIn-The-Loop (HITL) campaign covering 17 metrics across 20 scenarios at NPU dutylevels from 0 % to 100 %, analysed with a TOST equivalence + Jonckheere–Terpstratrend + Spearman correlation battery and a fully randomised validation experiment.Results. Equivalence testing accepts 339 of 340 metric–scenario pairs withinpre-specified operational margins. NPU inference latency is effectively deterministicat ∼7.9 ms per frame. MAVLink, QGroundControl, and jMAVSim require no modification, and the NPU module can be removed without disturbing flight control. Nocrashes, failsafe activations, or control-loop disruptions occur across the full dutyrange. Six recurring quality-attribute trade-offs are catalogued.Conclusions. Single-core processor integration of NPU acceleration and PX4flight control is feasible on current MCU-class hardware, given priority-based scheduling, spatial memory isolation, layered driver abstraction, and per-inference temporalarbitration. Direct on-target timing instrumentation and real-flight validation areidentified as the most critical extensions.