Power Efficient Core Allocation

Sammanfattning

Modern telecommunication systems are shifting towards utilizing commercial-off-the-shelf (COTS) hardware systems instead of relying on dedicated hardware solutions, necessitating efficient power saving strategies. This thesis presents a method for power gating idle processor cores in the form of a Linux kernel module and a controller which dynamically allocates and deallocates processor cores during a packet processing workload simulation. The controller was designed with minimal assumptions about the underlying system on and which metrics are available. Therefore, the controller allocates cores based on the current egress of packets and processing latency. Results from an Intel Broadwell platform show that the average power consumption during high workload levels can be reduced by 15 Watts and 44 Watts during idle periods. Simulations indicate that while in general, the core controller has very low impact on packet throughput, it faces challenges responding to sudden increase in packet ingress, particularly after idle periods. This results in a temporary spike in packet loss, which gets mitigated after ten workload generation cycles.