RFSoC-Based Digital Radar Target Simulator

Sammanfattning

This thesis designed, implemented, and evaluated a digital radar target simulator (RTS) based on a Radio Frequency System-on-Chip (RFSoC) platform for wide-band chirp-based radar applications. The objective was to investigate how range and velocity simulation could be achieved with low processing latency, fine delay resolution, and efficient hardware resource usage. The implemented simulator received an intermediate-frequency (IF) radar signal, processed it digitally, and retransmitted a modified signal representing a virtual radar target. Range simulation was implemented using a word-based memory delay, an integer-sample lane-shift stage, and a Farrow-structured finite impulse response filter (FSFF) for fractional-delay generation. Velocity simulation was implemented using a wide-band Doppler-shift generator synchronized to the received chirp. The system was evaluated through latency, delay, phase, Doppler, and resource utilization measurements. The results showed a mean net latency of 229.5 ns and a mean processing latency of 293.0 ns, corresponding to a minimum simulated distance (MSD) below the specified 100 m requirement. The delay measurements confirmed correct word-level and sample-level delay behavior, while the fractional-delay measurements showed close agreement with the theoretical phase shift. The wide-band Doppler generator produced an intra-chirp Doppler variation, but the measured Doppler ramp did not scale correctly with target velocity. The thesis concluded that the implemented architecture provides a low-latency and resource-efficient basis for digital radar target simulation, although further work is required to improve Doppler accuracy.