Signal Processing Chainsfor Modulation Systems : Design, Modeling and FPGA Implementation

Sammanfattning

This thesis examines the digital signal processing (DSP) chain in a modulation transmitter, focusing on the interpolation, resampling, and frequency mixing stages. There is a working system for 256-QAM in place. The goal is to model it and reduce the usage of FPGA DSP blocks without degrading performance. A DSP block is a hardware unit designed to efficiently perform arithmetic operations such as multiplying, adding, and accumulating digital signals. For interpolation, the system employs multistage structures combining half-band Type I linear phase FIR filters (designed using the Parks–McClellan algorithm) and polyphase decomposition to reduce computational load. Fractional delay resampling is implemented using a Farrow structure filter, optimized through minimax FIR filter design and a two-rate-based architecture. Frequency mixing is performed using Gauss's method for complex multiplication, which reduces the number of required real multipliers from four to three. A Python-based model simulates the entire signal chain and provides a platform to analyze resource usage under various selections of design parameters. Additionally, VHDL implementations of the interpolator and the complex multiplier were developed to evaluate their performance in real hardware, with special attention to finite word-length effects such as quantization noise, coefficient truncation, and overflow behavior. The results show that the optimized system achieves significant savings in DSP blocks (about 50\%) compared to the original implementation, while maintaining the required signal quality for 256-QAM transmission.