Superoptimization for the EMCA DSP : Adapting an LLVM IR Superoptimizer for a Production Compiler

Sammanfattning

Modern digital signal processors used in telecommunication infrastructure operate under strict performance, latency, and resource constraints, making compiler optimizations highly valuable. This thesis investigates how superoptimization can be adapted and integrated into the LLVM-based production compiler toolchain for the Ericsson Many Core Architecture Digital Signal Processor (EMCA DSP). The work focuses on identifying missed backend optimization opportunities in the compiler’s intermediate representation before final code generation, with particular attention to peephole optimizations, specialized DSP instructions, and the challenges introduced by a VLIW architecture. A prototype superoptimizer was developed by adapting the LLVM IR superoptimizer Souper to Ericsson’s internal compiler environment, Flacc. We evaluated the prototype on randomly selected EMCA DSP application files using static compiler metrics such as code size, instruction count, cycle count, and loop-weighted cycles, as well as dynamic benchmark measurements from simulation. The results show that superoptimization can discover optimization opportunities that the existing internal optimization layer misses. Under baseline Souper runs without specialized instructions enabled, we identified and verified 11 recurring peephole optimization patterns, spanning constant folding, algebraic simplification, redundancy elimination, and looped dependency removal; further distinctive patterns may remain discoverable with broader tracing. Across larger application-code experiments, the prototype produced consistent aggregate reductions in code size, instruction count, and cycle estimates. Support for selected specialized instructions, including multiply-accumulate and bit extraction operations, further improved the aggregate results, although some target-specific instructions caused regressions due to VLIW scheduling and parallelism constraints. Dynamic benchmarking confirmed a net performance improvement, but also showed that static cycle estimates only partially predict runtime behavior. The thesis concludes that an integrated superoptimizer is useful as an offline analysis tool for discovering and validating backend optimizations in a production compiler. However, its direct use in normal compilation is limited by high SMT-solving cost, incomplete awareness of VLIW scheduling, register pressure, instruction-level parallelism, and differences between static and dynamic execution behavior.