Understanding Intel E-core Prefetcher Behaviour through Performance Counters

Sammanfattning

As modern computational workloads become increasingly data-intensive, memory access latencyremains a primary bottleneck to performance. To mitigate this “Memory Wall”, processors utilisehardware prefetchers of varying complexity, from basic next-line fetchers, to advanced spatialpredictors to speculatively load data into cache. To prevent cache pollution and interconnect con-gestion, processors often employ static bandwidth throttling policies to clamp speculative traffic. The objective of this thesis is to empirically evaluate the performance characteristics of differentprefetching algorithms and their systemic interactions with bandwidth throttling mechanisms onthe Intel Crestmont microarchitecture. By using model-specific registers and physical performance monitoring unit telemetry, this the-sis isolated individual prefetcher algorithms (L1 Next-Line prefetcher, L2 streamer, and Adaptive Multi-Path), and then evaluated them across varying throttling profiles using the SPEC CPU 2017 benchmark suite. The results demonstrate that prefetcher efficacy is highly workload-dependent. While compute-bound workloads are largely insensitive to prefetcher configurations, memory-bound workloads expose a conflict coined the Throttling Paradox. In this context, the paradox is that the mechanism designed to optimise performance by limiting memory bandwidth, insteadleads to performance degradations on single threaded workloads. The findings suggest that it triggers demand-driven replacement by blocking early speculative requests and forcing the CPU to issue late, pipeline-stalling demand misses for the exact same data.