A Low Power Dual-path Sub-Sampling PLL Covering 2GHz-4GHz

Sammanfattning

Ring voltage-controlled oscillators (Ring VCOs) are widely used in clock generation because of their compact area and wide tuning range, but their high inherent phase noise limits their application in high-performance systems. To address this, this thesis presents a low-power dual-path sub-sampling PLL (SSPLL) covering a wide frequency range from 2GHz to 4GHz. To effectively suppress the phase noise from the Ring VCO, this design employs a sub-sampling phase detector and charge pump (SSPD/SSCP) architecture to drastically increase the bandwidth of PLL, and also reduce the in-band noise. Meanwhile, a dual-path topology is introduced to further widen the loop bandwidth. Furthermore, an Automatic Frequency Calibration (AFC) algorithm is adopted to accelerate the locking process. The proposed circuit is designed and simulated in a 65nm CMOS process. When operating at an output frequency of 2.05 GHz, the total power consumption is only 6 mW. The RMS jitter is optimized to 1.24 ps (integrated from 100KHz to 100MHz), and the phase noise reaches -111 dBc/Hz at 10 MHz offset.