A Pipelined Loop-Unrolled SAR ADC with Open-Loop Amplification

Sammanfattning

This thesis presents the analysis and design of a three-stage pipelined loop-unrolled successive approximation register (Lu-SAR) analog-to-digital converter (ADC) implemented in 65 nm CMOS technology. The ADC is designed to achieve high speed and good linearity under low supply voltage and limited power, targeting wireless communication and high-speed data acquisition applications. At the system level, inter-stage redundancy is used. The main non-idealities, including sampling distortion, comparator offset, capacitor mismatch, and open-loop amplifier nonlinearity, are analyzed and modeled. Open-loop residue amplifiers are adopted to improve speed and power efficiency, while digital background calibration is used to correct their gain and nonlinearity errors. A least-mean-square (LMS) based digital background calibration algorithm is developed to correct gain error, bit-weight deviation, and amplifier nonlinearity. Simulation results at both the behavioral and circuit level show that the proposed calibration can effectively restore the linearity. After calibration, the ADC achieves more than 60 dB SNDR and over 80 dB SFDR at 300 MS/s, which confirms the effectiveness of the proposed architecture and calibration scheme.