Design of a Mixer-First Receiver with Current-Mode Passive Mixer and Transimpedance Amplifier for High Linearity

Sammanfattning

This thesis presents the design and schematic-level simulation of a highly linear mixer-first receiver front-end implemented in CMOS, targeting improved robustness against strong input signals. The proposed architecture employs a current-mode passive mixer directly loaded by a low-impedance transimpedance amplifier (TIA) in order to minimize the voltage swing at the mixer output and thereby enhance linearity. To further protect the mixer core from large RF input voltages, resistive input matching is employed, trading off a portion of the noise performance for improved signal-handling capability. The receiver front-end comprises a current-mode passive mixer, a wideband TIA for current- to-voltage conversion, and a low-pass filtering network to suppress undesired mixer products such as LO feedthrough. The design is carried out in Cadence Virtuoso in 65nm technology, and the performance of individual blocks as well as that of the cascaded receiver chain is evaluated through schematic-level simulations. Key performance metrics include linearity (IIP3), input matching and gain, and noise figure. The impact of low mixer switch on-resistance, TIA loading, and resistive matching on the overall linearity and noise performance is analyzed and discussed. The results of this work aim to provide design insights into mixer-first receiver architectures that prioritize linearity and robustness. The linearity is simulated using two tones placed outside the receiver bandwidth to resemble the situation with strong interference in adjacent channels, resulting in an input referred third order intercept point equal to 32dBm. The noise figure was simulated to 15 dB, and each TIA consumed a power of 182mW from a 1.2V supply. The total power consumption of the receiver including LO buffers was 740mW.