Direct RF sampling ADC analog front-end for 6G

Sammanfattning

A time-interleaved ADC analog front-end is presented with a sampling rate of 64GS/s. It has a hierarchical architecture of 2-4-4 giving 32 separate channels. Each channel is constructed by an input buffer, 1st rank (T/H), sub-buffer, and 2nd rank T/H. The complimentary clocking generation consist of a 32GHz differential signal divided down using a CML divide-by-4 and DFF divide-by-4 architecture. The required duty cycles for the time-interleaved network were generated using gate logic. The SFDR and SNR ranges from 41dBc-34dBc and 38dB-31dB re- spectively within the FR3 band. In stable state, the total power consumption of the analog front-end is 484mW including the interleaving network and clock gen- eration. This was constructed using GlobalFoundaries 22FDX technology node. All simulations were done in Cadence Virtuoso environment.