Energy-Per-Inference Prediction for 1D CNNs on the ZCU104 FPGA

Sammanfattning

Background. Deploying a convolutional neural network on an FPGA for real-time industrial monitoring requires choosing among architectures that differ substantially in energy consumption, latency, and throughput. Determining the energy cost of a candidate architecture currently requires physical hardware access and extensive hardware benchmarking, making the exploration of large design spaces impractical. Objectives. This thesis investigates whether energy-per-inference (EPI) can be predicted from model architecture parameters alone, before hardware benchmarking begins, enabling energy-aware model selection without repeated board programming. Methods. A family of 23 deployable 1D CNN models spanning four orders of magnitude in parameter count was benchmarked on the AMD/Xilinx ZCU104 FPGA with a B4096 DPU configuration. A custom two-thread pipeline measured EPI, latency, and throughput across three independent repetitions. Gaussian process regression was trained after feature selection from a pool of 29 architecture-derived features, yielding one to two features per target. Results. Two principal findings emerged. First, EPI follows a power-law scaling relationship (E ∝ P0.749, R2 = 0.984), with sublinear latency scaling and a measured system-level power plateau at large model sizes. Together, these observations are consistent with a structural mismatch between image-optimized DPU hardware and short 1D time-series workloads. The GPR achieves lower-bound MdAPE of 13.8%, 12.6%, and 15.4% for EPI, latency, and throughput respectively, due to partial nesting of feature selection. Empirical coverage of the stated 95% prediction intervals is 95.7%, consistent with the nominal level at this sample size. Second, a previously undocumented compiler deployability boundary was discovered in Vitis AI that structurally identical models can fail to compile to a single DPU subgraph based solely on channel width, an effect not evident to the user before compilation is attempted. Conclusions. EPI can be predicted from model architecture parameters alone, before hardware benchmarking begins, with screening-level accuracy for architecture ranking and shortlisting. Inspection of compiled binaries indicates an undocumented Vitis AI channel-width boundary. Above this boundary, standard Conv1d operations may berepresented as operator decompositions that exceed the DPU instruction set boundary, causing CPU fallback that is not evident before compilation is attempted. Both findings are practically actionable. The predictor narrows the candidate architecture set before hardware access, and the compiler boundary makes empirical pre-flight verification a required step in any Vitis AI deployment pipeline. All measurement data and compiled model binaries are publicly released on Zenodo.