FPGA Implementation of a Non-Negative Least Squares Accelerator Using Floating-Point Arithmetic : A Fast Projected Gradient Approach

Sammanfattning

This thesis explores the implementation of a Non-Negative Least Squares accelerator onan FPGA. The implementation applies the Fast Projected Gradient algorithm, utilizing itsregular vector-matrix structure to achieve a high level of parallelism in the accelerator’score computations. In addition to achieving efficient parallel computation, particular emphasis is placed on the parameterizability and scalability of the hardware architecture. Furthermore, a competitive result in the aspect of resource usage and throughput comparedto existing implementations is of interest. The results of the implementation across theseareas are promising. Utilizing the FPGA’s ability to achieve parallel execution of the computational units. The number of computational units and input parameters of the designmatrix are highly configurable, satisfying the parameterizability and scalability requirements of the hardware architecture. Lastly, the synthesis results are competitive with otherimplementations in terms of resource utilization and throughput.