Evaluating pseudo-random SRAM for AI applications in GPU cache

Sammanfattning

General Purpose Graphics Processing Units (GPGPUs) have become the prevalent processor for AI/ML and other large computational problems because parallel processing has not reached a hardware limit, unlike single-threaded processing. The goal of the thesis is to investigate the suitability of a novel SRAM architecture for implementation in a GPU without extensive GPU architecture changes. This architecture features groups of SRAM cells called zones, which are leveraged to perform pipelined SRAM read operations to reduce dynamic energy consumption. This thesis examines the implementation of an energy-efficient SRAM in GPU caches and analyzes its energy saving and performance under AI/ML work loads in a GPU. GPGPU-Sim [1] simulator was used to run all the benchmarks. The simulator was modified to output all memory accesses made to L1 and L2 cache. Thereafter, the memory accesses were used by the software cache model to analyze the performance and energy of all the workloads run. Hybrid SRAM implementations with a small capacity conventional SRAM in tandem with the Pseudo-random SRAM (PR-SRAM) were investigated to check penalty cycles and reduction in dynamic energy consumption. A penalty cycle is a stall in the pipeline caused by repeated access to a specific zone. The penalty cycle rate is the number of penalty cycles per 100 accesses. The hybrid implementation featured a 33% increase in energy consumption versus the pure PR-SRAM implementation. This increase in energy consumption was the cost of reducing the penalty cycle rate by 43%. The effect of cache replacement policy on the performance of the hybrid design was also investigated, Least Recently Used (LRU) achieved the lowest penalty cycle rate. The gains were also measured against the complexity required to perform necessary operations with the hybrid cache.