Functional Verification of SPI Controller using UVM

Sammanfattning

Radio Frequency Integrated Circuits (RFICs) play a crucial role in modern wireless communica- tion systems. However, they can achieve high performance only when their internal registers are dynamically and precisely configured. To maintain reliable control while operating in complex multi-antenna environments, several interface techniques have been developed, among which the Serial Peripheral Interface (SPI) control module is one of the most critical bridges for translating system bus requests into SPI transactions. In this thesis, we designed and analyzed a comprehensive Universal Verification Methodology (UVM) environment for an SPI_CTRL module consisting of a dual block random access memory(BRAM) architecture and eight independent SPI channels. This work began with the development of a verification architecture to ensure the testbench effectively stimulates the design’s internal request FIFO and state machines. Based on this design, we evaluated its behavior across various clock domain crossing (CDC) conditions and continuous read/write requests, gaining insight into its scheduling performance and functional completeness. This work evaluates the impact of concurrent high-speed AXI4-Lite transactions on the SPI_CTRL’s stability. With the increasing demand for high integration and flexibility in wireless systems, handling massive parallel data translation has become an essential requirement. However, dynamic operating conditions and varying request timings introduce complex corner cases that challenge the adaptability and reliability of traditional directed testing methods. This thesis analyzes the functional coverage of the SPI_CTRL design under varying request traffic and checks if all logical anomalies and timing violations can be eliminated by employing the UVM framework.