Low-Latency Resampling Architectures for Particle Filters on FPGA

Sammanfattning

As wireless communication systems evolve toward 6G and joint communication and sensing paradigms, emerging applications impose stringent low-latency constraints on target tracking systems. Within the hardware implementation of particle filters, the traditional systematic resampling algorithm suffers from global data dependencies and sequential memory accesses, creating a fundamental performance bottleneck. To address this latency issue, this report designs, implements, and evaluates two distinct resampling architectures on an FPGA platform. The first design is an optimized sequential architecture that utilizes pre-fetching logic to effectively mask the inherent read latency of the on-chip memory. To completely break the sequential bottleneck, the second design introduces a parallel architecture based on the Metropolis-Hastings algorithm. By employing an array of independent processing elements and a decentralized memory topology, combining private working memories with dual-port shared read-only memories, this architecture eliminates global data dependency and avoids the routing congestion and stall penalties associated with traditional crossbar switches. Hardware results at a 100 MHz clock frequency demonstrate that the optimized sequential architecture achieves an execution time of 81.98 μs. Furthermore, the parallel architecture utilizing 16 PEs when dynamically downscaled to 4 iterations reduces the execution latency to 10.49 μs delivering a 15.6 times speedup compared to the standard baseline. While the parallel approach consumes more Block RAM and digital signal processing resources and exhibits a bounded statistical degradation, this trade-off provides a mathematically sound and scalable hardware solution to meet the real time demands of next generation applications.