Modular machine learning based circuit design

Sammanfattning

In traditional circuit design a pre-selected circuit topology is optimized through timeconsuming parameter sweeps to satisfy a design criteria. A newly introduced designconcept instead utilizes machine learning models to predict the transfer functionof a given circuit structure, together with a genetic algorithm to generate a circuitbased on wanted scattering parameters.The concept of machine learning in circuit design, however, has its drawbacks. Onenotable drawback is that the circuits generated from the model are all of the samesize the model was trained on, leading to scalability issues. To overcome this problemthis thesis evaluated whether or not it is possible to use a machine learning modeltrained on a dataset of smaller 9 × 9 circuits to create a larger modular circuit, consisting of four modules. The generated modular circuits were assessed by comparingthe predicted scattering parameters from the optimization to the pre-selected targetparameters. Additionally, simulations were performed on the generated circuits andthe results were compared with the predicted parameters. The thesis also investigated if the implementation of a via fence could help isolate the modules fromeachother to reduce electromagnetic interference and improve performance. Thedifferences in time efficiency between the two cases were also compared.The results show that the modular concept works to a high degree. Based onsimulation results, the root mean square error for the scattering parameters forthe non-via fence model was 0.05934 and for the via fence model it was 0.04677.Adding a via fence improves the model predictions slightly and further improvesthe simulated circuits significantly. The results for the circuit designs with a viafence, over 100 generated circuits designs, were 13 % more accurate than the circuitdesigns without a via fence. However, this came at the cost of increased simulationtime, as circuits using a via fence took a considerably longer time to simulate.