Optimized Hardware Implementation of Linear Transformations

Sammanfattning

Adders are fundamental building blocks in Application-Specific Integrated Circuits (ASICs) and play a central role in the arithmetic datapaths of modern digital signal processing systems. Operations such as finite impulse response (FIR) filtering, beamforming, and signal combining rely on evaluating weighted sums of multiple inputs. These computations can be expressed as linear combinations and are typically implemented using multiply-add structures followed by multi-operand adder trees. Since such arithmetic structures are replicated extensively throughout Digital Front-End (DFE) ASICs for 5G and emerging 6G systems, even small improvements in their implementation can translate into significant reductions in silicon area and power consumption. This thesis investigates the optimal pipelining and decomposition of multi-input arithmetic aggregation circuits with the objective of minimizing area, dynamic power, and leakage power. A parameterized library of arithmetic building blocks was developed that covers variations in depth, width, and architecture to serve as the design space for the optimization phase. To evaluate the implementation cost of each building block, an automated RTL-to-gate synthesis and power estimation flow was established, generating a characterization dataset across multiple design points. To further assess design robustness across operating conditions, the exploration was extended to include multiple supply voltages and clock frequencies. Based on this dataset, a dynamic programming framework was developed to determine cost-efficient hierarchical implementations of large summation structures. The proposed methodology decomposes a target aggregation problem into two stages: an initial reduction stage composed of arithmetic compression blocks, followed by a consolidation stage that combines the intermediate results using a selected adder architecture. The optimization framework evaluates alternative partitions and architectural choices while accounting for synthesis-derived area and power costs. The results demonstrate that the proposed framework can efficiently identify implementation configurations that provide favorable area-power trade-offs while balancing the competing objectives of silicon area, dynamic power, and leakage power. The developed methodology provides a systematic approach for exploring arithmetic architectures in ASIC design and can support the implementation of energy-efficient signal-processing hardware for future communication systems.