Optimizing Neural Network Inference : A RISC-V Co-Processor Framework for 5G Communications

Sammanfattning

Artificial Intelligence (AI) is advancing rapidly, with neural network inference continually being optimized for high performance, compact size, and low power consumption. This progress creates diverse opportunities for integrating AI capabilities into the Reduced Instruction Set Computing - V (RISC-V) hardware ecosystem. Originating from UC Berkeley, RISC-V emphasizes a simplified Instruction Set Architecture (ISA) that enhances execution efficiency and scalability, making it suitable for the varied computational demands of neural network processing across different environments. In this research, we utilize the Spike Instruction Set Simulator (ISS) to evaluate the performance of the RISC-V architecture. We propose integrating a RISC-V core with a custom co-processor, optimizing and evaluating a Neural Processing Unit (NPU) architecture based on the RISC-V core. This evaluation uses a pre-trained neural network model provided by the Huawei HiSilicon BB IC team, aimed at efficiently executing neural networks within embedded 5G modems. The proposed architecture incorporates three types of Tightly-Coupled Memory (TCM)s to minimize data access to the main memory. Additionally, it employs a row-stationary-like data flow method within the Process Element (PE) array. This thesis details the matrix operation logic within the PE array of the RISC-V core architecture, the methods for executing and optimizing neural network models on RISC-V, and the results of our evaluations.