Specific Instructions Set for Neural Network Acceleration Based on Multiple RISC-V Cores

Sammanfattning

Artificial Intelligence (AI) has been applied in next-generation channel estimation and multiple-input multiple-output (MIMO) design in cellular communication modems. The requirements on high speed, small footprint and low power consumption makes inference of even medium sized neural networks challenging. General accelerators do not achieve optimal performance, and existing instruction set architectures (ISAs) lack direct support for these specific applications. In this paper, we propose a multi-core architecture integrating a RISC-V core with a custom coprocessor to accelerate selected neural networks and define its ISA for memory access, computation and configuration. The design includes three types of tightly coupled memories (TCMs) positioned near the processing engine to realize cross-layer computation and overlap memory access cycles, addressing the memory access speed limitations in neural network computations. The dataflow, similar to the row stationary method, optimizes performance by maximizing local data reuse, thereby reducing costly data movement to main memory. The coprocessor communicates via the Rocket Custom Coprocessor (ROCC) interface with the main processor. For evaluation, a pre-trained NN is used in the Spike ISS simulator. Our design speeds up execution cycles by 36% for graph neural networks through efficient local data transfers between TCMs, achieving significantly higher performance compared to a general RISC-V core when processing 2-dimensional matrix convolution and multiplication.