Pipeline ADC PN-Dither LMS Background Calibration: FPGA and ASIC Digital Back-End Implementation

Sammanfattning

This thesis presents a complete digital back-end implementation of a PN-dither least-mean-squares (LMS) background calibration scheme for a 12-bit, 500 MS/s pipeline analog-to-digital converter (ADC). The target converter, designed by a parallel analog project, comprises four 3-bit stages and a 4-bit final flash stage; its actual inter-stage gains depart substantially from their nominal values, reducing the effective number of bits (ENOB) of the uncalibrated output to 4.19 bits. The back-end injects a small pseudo-noise dither at the residue path of each calibrated stage and uses a one-tap LMS update to track the gain errors in real time. A division-free reconstruction datapath, obtained by algebraic rearrangement of the standard reconstruction equation, recovers the calibrated output using only multiplications and additions. A parametric study of the gain-accumulator bit width identifies a stochastic-quantisation regime that informs the choice of a 24-bit accumulator (S3.20 format), trading 0.26 bits of ENOB for a 53% reduction in look-up table count relative to a full-precision reference. The same Verilog source has been carried through both an FPGA verification flow and an ASIC physical-implementation flow. On a Xilinx Artix-7 XC7A100T the design closes timing at 58.8MHz with 721 LUTs, 577 flip-flops, 11 DSP48 blocks, and 113mW of total power. On a 65 nm CMOS process the placed-androuted layout occupies 0.031mm2 and dissipates 2.07mW under default activity— a factor of 55× lower than the FPGA target. The achieved steady-state ENOB of 7.20 bits exceeds the project objective of 7 bits and demonstrates that a heavily resource-optimised digital calibration back-end can match the spectral performance of a full-precision baseline in production-silicon form.