RTL Restructuring Methodology to Overcome Physical Design Challenges in Complex IPs

Sammanfattning

The continued scaling of complementary metal-oxide semiconductor (CMOS) technology has fundamentally altered the relationship between register-transfer level (RTL) design and physical implementation in application-specific integrated circuits. The traditional sequential treatment of these two activities is no longer adequate for meeting the power, performance, and area targets of modern system-on-chip designs, resulting in costly iterations between the frontend and backend design teams that are often compounded by manually executed RTL restructuring without formal validation. This thesis develops a robust and validated RTL restructuring methodology that addresses this misalignment. The methodology is structured into three sequential phases covering physically-aware RTL and collateral restructuring, formal validation, and re-implementation with comparative metric analysis. Two complementary flows are derived from it, that is, a Backend Partitioning Flow targeting the physical design and integration team, which constitutes the primary contribution of the work, and a Frontend Design Exploration Flow targeting the RTL and IP design teams. The methodology is applied to two complex industrial intellectual property (IP) blocks. The first investigation, on an Ethernet Switch IP characterized by a large IO count, long tool runtimes, and heavy pin congestion, demonstrates the flow’s ability to support the discovery of new partitioning solutions. The second investigation, on a CPU IP and an Interconnect IP, demonstrates the flow’s ability to rapidly and reliably apply a known partitioning solution by merging the two IPs into a single combined partition. The merged partition matches the better of the two original partitions on worst-case timing slack while substantially resolving the timing problems of the more problematic partition, at the cost of an expected increase in tool runtime, with functional correctness preserved as confirmed by formal logic equivalence checking. Both investigations compress restructuring efforts that would typically require weeks of manual engineering work into a matter of hours. The first investigation additionally revealed restructuring scenarios that fell outside the scope of the available EDA tooling, and an AI-supported restructuring approach was explored as a complement to the methodology, delivering substantial improvements in IO count and runtime on the same design.