Side-Channel Attacks Using On-Chip Reliability Instruments

Sammanfattning

Modern integrated circuits contain extensive on-chip instrumentation—Ring Oscillators (ROs), temperature sensors, voltage monitors, and delay-measurement circuits—originally intended for reliability monitoring and process calibration. The same physical sensitivity that makes these instruments effective sensors also makes them potential side-channel receivers. An adversary who can place or exploit such instrumentation near sensitive logic may be able to recover secret-dependent information without requiring external measurement equipment or physical probing. This threat is relevant across FPGA, ASIC, and SoC platforms, yet the boundary conditions under which on-chip instrumentation can reliably leak key information remain incompletely characterised. This study uses a Xilinx Artix-7 FPGA as a controllable proof-of-concept platform to examine how key-bit observability degrades as the coupling path between a secret source and an on-chip RO listener is systematically weakened. Three completed experimental families span the coupling continuum from a direct electrical connection through a GPIO-level threshold-limited path to pure physical proximity without intentional logical wiring. The direct-connection baseline matches 255 of 256 streamed AES-256 key-bit decisions (99.61%) using on-chip digital capture alone. The GPIO-level path shows an abrupt threshold-limited failure: with a 400 Ω pull-down, agreement remains at 100% for 0–300 Ω series resistance and collapses to an all-zeros classifier at 400 Ω and above, where the returned voltage no longer crosses the FPGA input-buffer threshold. The proximity-only matrix—24 conditions covering three placement distances and eight RO lengths—shows that calibrated key-bit separability is strongly distance- and RO-length-dependent: near placement reaches 99.61% supervised separability at N=35 and 100% for N=45–75, while medium and far placement remain partially distinguishable or weak. The central finding is that on-chip reliability instruments can act as effective side-channel receivers not only through explicit electrical paths but also, under favourable physical conditions, through unintended proximity coupling. The practical risk is therefore not limited to designs containing deliberate Trojan wiring; it extends to any scenario in which an attacker can place or activate monitoring instrumentation near sensitive routing. The results motivate treating the placement and configuration of on-chip reliability instruments as security-relevant design decisions, enforcing physical separation between cryptographic key nets and untrusted instrumentation structures, and including routing-level proximity analysis in security verification flows.