UVM-Based System Verification with Assertions and Coverage Techniques : Coverage driven verification environment with formal unreachability analysis

Sammanfattning

This thesis presents the design and implementation of a UVM-based verification environment for the Minimal OpenRISC System-on-Chip (MinSoC). The MinSoC architecture integrates the OpenRISC 1200 (OR1200) CPU, Wishbone interconnect, on-chip memory, UART, and Ethernet peripherals. The work targets implementation on the Altera Stratix III FPGA platform. The environment uses a reusable, coverage-driven UVM framework to verify SoClevel interactions. The developed environment employs SystemVerilog UVM components such as agents, drivers, monitors, and scoreboards to achieve modularity and reusability. A hierarchical verification plan defines 38 verification points across two major peripherals: UART and Ethernet. Constrained-random stimulus generation and functional coverage verify communication between the CPU, memory subsystem, and peripherals, ensuring compliance with the Wishbone protocol and peripheral specifications. The verification environment achieves more than 70% code coverage of reachable design functionality and functional coverage across verified subsystems is addressed by implementing cover groups. Formal unreachability analysis mathematically proved that significant portions of uncovered code are structurally unreachable due to design parameters and architectural constraints. The results show that the UVM-based framework, enhanced with formal coverage analysis, provides measurable verification completeness through functional and code coverage metrics.