A Three-Stage SAR-Assisted Pipeline ADC for High-Speed and High-Linearity Applications

Sammanfattning

The performance of future technologies such as wireless communication, industrial automation, robotics, artificial intelligence, and intelligent sensing systems critically depends on analog-to-digital converters (ADCs), which serve as the essential interface between the analog and digital domains. State-of-the-art ADCs often employ time-interleaving to overcome the speed limitations of single-channel architectures. However, this approach introduces significant design challenges, including mismatches, crosstalk, and timing discrepancies between channels, which become more pronounced with an increasing number of channels. Therefore, enhancing the speed of individual ADC channels without compromising accuracy and power efficiency is a crucial objective. The successive-approximation-register (SAR)-assisted pipeline archi- tecture extends the application of SAR ADCs by incorporating residue amplification between two SAR-ADC stages to achieve high energy efficiency at increased sampling rates. However, the speed is limited compared to multiplying digital-to-analog converter (MDAC)-based pipeline architectures, partly due to the required high-resolution ADC per stage. To overcome this limitation, a three-stage pipeline 12-bit ADC is proposed consisting of three SAR-ADC stages with resolutions of 4, 4, and 6 bits, respectively, incorporating 1-bit interstage redundancy. The design aims to enhance speed compared to the traditional two-stage variant while maintaining high linearity and high energy efficiency. The ADC integrates two fully differential ring amplifiers (RAMPs) with 1/gm loading to achieve fast amplification times with high linearity and to provide process, voltage, and temperature robustness. Each stage employs a comparator consisting of a Floating Inverter Amplifier (FIA)-based pre-amplifier and a strong ARM latch as the second stage, utilizing dynamic biasing to improve energy efficiency while maintaining high speed. Additionally a charge redistributution digital- to-analog converter with the early reset merged capacitor switching algorithm is implemented in each stage. The work was carried out in Cadence Virtuoso at a schematic level. The total power consumption of the ADC is 3.0 mW at a sampling rate of 800 MHz. Transient simulations, in conjunction with the Fast Fourier Transform, show that when the ADC is subjected to a differential input voltage of 400 mVpp at close to Nyquist rate input frequency of 395.6 MHz, it achieves a Spurious-Free Dynamic Range (SFDR) of 90.64 dBc and a Signal-to-Noise-and-Distortion Ratio (SNDR) of 64.66 dB. While developed at a schematic level with ideal switches and Verilog-A logic, the design demonstrates significant potential for high-speed, high-linearity applications, benefiting from the reduced number of residue amplifiers due to the SAR-ADC stages.