Interfacing DSP Architecture Compiler and Reinforcement Learning Based Instruction Scheduler

Sammanfattning

In modern compiler design, instruction scheduling in the compiler backend plays an important role in producing high-quality assembly code. Most existing optimizations for instruction scheduling need to be fine-tuned to adapt to different targets. Optimizing the instruction scheduling algorithm is not straightforward. The instruction scheduler has to produce high-quality schedules within the constraints of dependencies between instructions, the limitations of computational units, and physical registers. Although there have been previous studies on solving task scheduling problems using machine learning or using machine learning to guide compiler optimization, using machine learning methods to optimize instruction scheduling is still an area that needs further study. Given a pre-trained RL-based instruction scheduler, we have this question: how to design an interface that can efficiently connect the RL-based instruction scheduler to a compiler and compile radio application test programs in real-time? This master’s thesis focuses on optimizing the instruction scheduling phase in the compiler by designing an interface that connects a reinforcement learning-based scheduler to an LLVM-based compiler. In this work, we designed and implemented an interface between a reinforcement learning-based scheduler and compiler to achieve better code execution speed. We proposed a mechanism to communicate between the compiler and the reinforcement learning-based scheduler, which includes programs that control the communication between the compiler and the scheduler using a file-based methodology. We also proposed an efficient method to access data from the compiler using a custom format. We conducted experiments using this interface with benchmark programs to evaluate the code execution time. The compilation result from the system passed all the benchmark tests. It demonstrated that the interface successfully applies the RL-based instruction scheduler to the compiler and compiles radio application test programs in real-time.